1. Field of the Invention
The present invention relates to a semiconductor integrated logic circuit with sequential circuits which has an information holding function in a sleep mode.
2. Description of the Related Art
Conventionally, in a semiconductor integrated logic circuit, a system having a transistor circuit structure is adopted to satisfy a high speed operation in an active mode and low power consumption in a sleep mode. Especially, the semiconductor integrated logic circuit has an information holding function such that a memory data of the sequential circuit is not destroyed at the time of the sleep mode.
For example, the following technique is disclosed in the Japanese Patent No. 2,631,335 (Japanese Laid Open Patent Application (JP-A-Heisei 06-029834). That is, in a semiconductor integrated logic circuit can operate at high speed, the power is supplied through a higher threshold type transistor to block off a leakage current at the time of the sleep mode. Also, a bistable circuit composed of higher threshold type transistors is added to the sequential circuit and the power is directly supplied to the higher threshold type transistors. Thus, the blocking-off of a leakage current and the avoidance from destruction of the memory data at the time of the sleep mode is attained.
FIG. 1 is a circuit diagram which shows a conventional example of the semiconductor integrated logic circuit with sequential circuits, which has an information holding function at the time of the sleep mode.
As shown in FIG. 1, a control transistor HP1I which is composed of a p-channel type MOSFET with a high threshold value. The control transistor HP1I is connected with a higher potential side actual power supply line VDD at the source electrode and a higher potential side quasi power supply line VDDV at the drain electrode. Thus, the electric connection between the higher potential side actual power supply line and the higher potential side quasi power supply line is set to the conductive state or the blocking-off state in response to a sleep mode switching signal SL which is applied to the gate electrode. Also, a control transistor HN1I which is composed of an n-channel type MOSFET with a high threshold value. The control transistor HN1I is connected with a lower potential side actual power supply voltage GND at the source electrode and a lower potential side quasi power supply voltage GNDV at the drain electrode. Thus, the electric connection between the lower potential side actual power supply line and the lower potential side quasi power supply line is set to the conductive state or the blocking-off state in response to an inverted sleep mode switching signal SLB which is applied to the gate electrode. In this case, the inverted sleep mode switching signal SLB is the signal which is obtained by inverting the sleep mode switching signal SL, and is sent out from a sleep mode control circuit which is not illustrated.
A CMOS circuit group which is composed of the inverter circuits INV1I and INV2I which are composed of lower threshold type transistors. The inverter circuits INV1I and INV2I performs the buffering operation of data signals D1B and D2B which are supplied to the latch circuits 10A and 10B, respectively. The inverter circuit INV1I is composed of an n-channel type MOSFET as a lower threshold value transistor and a p-channel type MOSFET as a lower threshold value transistor. The gate electrodes of the respective transistors are connected in common and the data signal D1B is supplied thereto. The drain electrodes of the respective transistors are connected in common and function as an input terminal of the latch circuit 10A. The inverter circuit INV2I is composed of an n-channel type MOSFET as a lower threshold type transistor and a p-channel type MOSFET as a lower threshold type transistor. The gate electrodes of the respective transistors are connected in common and data signal D2B is supplied thereto. The drain electrodes of the respective transistors are connected in common and function as an input terminal to the latch circuit 10B.
Also, the source electrode of the p-channel type MOSFET with the lower threshold value in the inverter circuit INV1I is connected with the higher potential side quasi power supply line VDDV which supplies a higher potential side the quasi power supply voltage through the drain electrode of the control transistor HP1I. Also, the source electrode of the n-channel type MOSFET with the lower threshold value in the inverter circuit INV1I is connected with the lower potential side quasi power supply line GNDV which supplies a lower potential side quasi power supply voltage through the drain electrode of the control transistor HN1I.
Moreover, the structures of the latch circuits 10A and 10B of the sequential circuits have the information holding function at the time of the sleep mode in FIG. 1. The latch circuits 10A and 10B will be described.
The latch circuit 10A is composed of the transfer gates TM1A and TM2A and three inverter circuits INV1A, INV2A and INV3A. The transfer gate TM1A is composed of a n-channel type MOSFET as a lower threshold type transistor and a p-channel type MOSFET as a lower threshold type transistor. The source electrode of one of the transistors and the drain electrode of the other of the transistors are connected in parallel in an alternate manner. One of the electrodes of the transfer gate TM1A is connected with an output terminal of the inverter circuit INV1I and the other electrode thereof is connected with the input terminal of the inverter circuit INV1A.
Moreover, a clock signal .phi. is applied to the gate electrode of the n-channel type MOSFET as the lower threshold type transistor in the transfer gate TM1A. An inverted clock signal *.phi. which is the inverted signal of the clock signal .phi. is applied to the gate electrode of the p-channel type MOSFET as the lower threshold type transistor.
The transfer gate TM2A and the transfer gate TM1A have the same structure and are bidirectional. One of the electrodes of the transfer gate TM2A is connected with the input terminal of the inverter circuit INV1A and the other electrode thereof is connected with the ago output of the inverter circuit INV2A. It should be noted that the transistors of the transfer gate TM2A may be lower threshold type MOSFETs or high threshold type MOSFETs.
The inverter circuits INV1A, INV2A and INV3A have the same structure as those of the inverter circuits INV1I and INV2I, and each of transistors of the inverter circuit INV1A is an MOSFET with the lower threshold value. Each of the transistors of the inverter circuits INV2A and INV3A is an MOSFET with the high threshold value.
Also, the control transistor HP1A which is composed of a p-channel type MOSFET with the high threshold value sets the electric connection with the drain electrode to the conductive state or the blocking-off state in response to the mode switching signal SL. Also, the control transistor HN1A which is composed of an n-channel type MOSFET with the high threshold value, is connected with the lower potential side actual power supply voltage GND at the source electrode. The control transistor HN1A sets the electric connection with the drain electrode to the conductive state or the blocking-off state in response to the inverted sleep mode switching signal SLB applied to the gate electrode thereof.
Also, the source electrode of the p-channel type MOSFET with the lower threshold value in the inverter circuit INV1A is connected with the drain electrode of the control transistor HP1A. The source electrode of the n-channel type MOSFET with the lower threshold value in the inverter circuit INV1A is connected with the drain electrode of the control transistor HN1A. Also, the inverter circuit INV3A is connected with the inverter circuit INV1A in parallel. The inverter circuit INV3A is different from the inverter circuit INV1A in that the inverter circuit INV3A is directly supplied with a power supply voltage from the higher potential side actual power supply line VDD and the lower potential side actual power supply line GND. The power supply voltage does not pass through the control transistor such as the control transistor HP1A as the p-channel type MOSFET with the high threshold value and the control transistor HN1A as the n-channel type MOSFET with the high threshold value.
The output terminals of the inverter circuits INV1A and inverter circuit INV3A are connected in common and functions as the output terminal of the latch circuits 10A to send out the latch output signal Q1B to the subsequent stage of the circuit. Also, the output terminals of the inverter circuits INV1A and INV3A which are connected in common are connected with the input terminal of the inverter circuit INV2A. Also, the inverter circuit INV2A is composed of two MOSFETs as the higher threshold type transistors, like the inverter circuit INV3A. Moreover, the inverter circuit INV2A is directly supplied with the power supply voltage from the higher potential side actual power supply line VDD and the lower potential side actual power supply line GND.
Next, the operation of the latch circuit 10A shown in FIG. 1 as the sequential circuit which has the information holding function at the time of the sleep mode will be described.
The data signal D1B is inverted by the inverter circuit INV1I. Thus, the data signal supplied to the latch circuits 10A is taken in by the transfer gate TM1A at the timing of the clock signal .phi. and the inverted clock signal *.phi. which are supplied to the transfer gate TM1A and is sent out to the inverter circuits INV1A and INV3A. The data signal supplied from the transfer gate TM1A to the inverter circuit INV1A is possible to be taken in only when the power supply voltage is supplied to the inverter circuit INV1A in response to the sleep mode switching signal SL and the inverted sleep mode switching signal SLB.
The output signals from the inverter circuits INV1A and INV3A are sent out to the subsequent stage of the circuit as the output signal Q1B of the latch circuit and is sent out to the inverter circuit INV2A. The output signal from the inverter circuit INV2A is sent out to the transfer gate TM2A. The transfer gate TM2A sends out the output signal of the inverter circuit INV2A to the input side of the inverter circuits INV1A and INV3A at the timing of the clock signal .phi. and the inverted clock signal *.phi.. Thus, a latching operation of the data signal is performed.
In case of an active mode in which the sleep mode switching signal SL with a low potential (SL="0") and the inverted sleep mode switching signal SLB with a high potential (SLB="1") are applied, the control transistors HP1A and HN1A are set to the conductive state. The sequential circuit functions as the high-speed latch circuit by the transistors of the inverter circuits INV1A, INV2A and INV3A, and the transistors of the transfer gates TM1A and TM2A.
Next, in case of the sleep mode in which the sleep mode switching signal SL with the high potential (SL="1") and the inverted sleep mode switching signal SLB with the low potential (SLB="0") are applied, the control transistors HP1A and HN1A are set to the non-conductive state to block off the supply of the power supply voltage to the inverter circuit INV1A. In this case, if the state in which the clock signal .phi. with the low potential (.phi.="0") and the inverted clock signal *.phi. with the high potential (*.phi.="1") are applied is fixed in advance and an operation mode is switched to the sleep mode (SL="1" and SLB="0"), a bistable circuit holds data. At this time, the bistable circuit is composed of the inverter circuit INV3A which is connected with the inverter circuit INV1A in parallel and the inverter circuit INV2A through the transfer gate TM2A which is in the conductive state. Therefore, the internal state of the latch circuit is never destroyed.
Also, in the sleep mode (SL="1" and SLB="0"), the inverter circuit INV1A which is composed of the lower threshold type transistor is supplied with the power supply voltage through the control transistors HP1A and HN1A with the high threshold values in the blocking-off state. Therefore, the sub-threshold leakage current never increases power consumption.
Also, the power supply voltage is directly supplied to the inverter circuits INV2A and INV3A. However, the inverter circuits INV2A and INV3A are composed of the high threshold type transistors. Therefore, in the stationary state, the power consumption due to the sub-threshold leakage current never increases.
It should be noted that the latch circuit 10B has the same structure as the latch circuit 10A except for the point that the data signal D2B is inverted by the inverter circuit INV2I and the output signal of the latch circuit 10B is a signal Q2B.
In the conventional sequential circuit shown in FIG. 1, there is a problem in that there is a combination of circuits in which the power consumption due to the sub-threshold leakage current increases in spite of the sleep mode (SL="1" and SLB="0"). The reason why the above-mentioned problem is caused in the conventional semiconductor integrated logic circuit shown in FIG. 1 which has the information holding function at the time of the sleep mode will be described.
In FIG. 1, in the case that the sleep mode switching signal SL with the high potential (SL="1") and the inverted sleep mode switching signal SLB with the low potential with (SLB="0") are applied, i.e., in the sleep mode, the control transistors HP1I and HN1I and the control transistor HP1A and HN1A are set to the blocking-off state. In this case, the clock signal .phi. (.phi.="0") of the low potential and the inverted clock signal *.phi. (*.phi.="1") of the high potential are held at the applied state. Also, as the internal data holding states of the latch circuits 10A and 10B at that time, the output of the inverter circuit INV2A is in the "1" state (therefore, the output of the inverter circuit INV3A is in the "0" state), and the output of the inverter circuit INV2B is in the "0" state (therefore, the output of the inverter circuit INV3B is in the "1" state). Moreover, it is supposed that an operation mode is switched to the sleep mode (SL="1" and SLB="0").
When the semiconductor integrated logic circuit shown in FIG. 1 is in the above-mentioned state, the DC current which is caused by the sub-threshold leakage current flows along the route shown by the thick arrow line in FIG. 1 from the higher potential side actual power supply line VDD to the lower potential side actual power supply line GND. That is, the inverter circuit INV2A which has the input state of "0" and the output state of "1" functions as the supply source of the leakage current. In this case, the leakage current passes through the transfer gate TM2A in the conductive state, passes through the transfer gate TM1A which has a large sub-threshold leakage current because it is composed of a lower threshold type transistor although it is in the non-conductive state, passes through the transistor of the n-channel type MOSFET of the inverter circuit INV1I which has a large sub-threshold leakage current because it is composed of a lower threshold type transistor although its state is unclear, further passes through the lower potential side quasi power supply line, passes through the transistor of the n-channel type MOSFET of the inverter circuit INV2I which has a large sub-threshold leakage current because it is composed of a lower threshold type transistor although it is unclear that its state is in the conductive state or non-conductive state, passes through the transfer gate TM1B which has a large sub-threshold leakage current because it is composed of a lower threshold type transistor although it is in the non-conductive state, and passes through the transfer gate TM2B which is in the conductive state. Finally, the inverter circuit INV2B which has the input state of "1" and the output state of "0" functions as a demand source of the leakage current.
As described above, in the conventional example of the latch circuit 10A or 10B shown in FIG. 1 which has the information holding function at the sleep mode, power consumption due to the sub-threshold leakage current never increases, as long as the latch circuit 10A or 10B exists independently inside the semiconductor integrated logic circuit.
However, there is a problem in that two or more latch circuits such as the latch circuits 10A and 10B increases the power consumption due to the sub-threshold leakage current through the control transistors which are composed of p- and n-channel type MOSFETs with high threshold values such as the control transistors HP1I and HN1I, by means of another CMOS logic circuit to which the power is supplied from the higher potential side power supply and the lower potential side power supply, i.e. the inverter circuits INV1I and INV2I.
In conjunction with the above description, a logic circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-29834). In this reference, a low threshold logic circuit 20 is supplied with power from a first power supply line through a high threshold transistor TS1 and from a second power supply line through a high threshold transistor TS2. Therefore, when the transistors TS1 and TS2 are set to the OFF state, any current does not flow in the low threshold logic circuit. Also, since the threshold of the low threshold logic circuit is not necessary to be decreased, a propagation delay can be made small.
Also, a MOSFET circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-121152). In this reference, MOSFET circuits (111 and 112) are connected between a CMOS circuit group (3) with a low threshold voltage and the power supply voltage (VDD) and between the CMOS circuit group (3) and the ground as power supply control circuits to control a wait state and an operating state. MOSFETs (M1 and M3) with a high threshold value of the. MOSFET circuits (111 and 112) are applied with back gate biases from MOSFETs (M2 and M4) with a low threshold voltage to block off a current between a back gate terminal and a gate terminal.
Also, a sense amplifier circuit is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 9-274797). In this reference, a PMOS transistor (50) and an NMOS transistor (52) as switches and a level shifter are added to a sense amplifier circuit of a semiconductor memory. A first switch control signal ACTB and a second switch control signal ACT are generated by the level shifter, and a signal is level-shifted to a predetermined level and then supplied to the PMOS transistor (50) and the NMOS transistor (52).
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-54693). In this reference, when a power is turned on, a fault address determining circuit (30) generates a redundancy determination signal YR and a fault address (A30). A Y address decoder (24) decodes the fault address (A30) to supply the decoding result to a transfer gate (23) and a redundancy latch circuit (32) which is provided for fault bit line pair (BL1a, BL1b). Thus, the redundancy latch circuit (32) is selected to set switches (33a, 33b) to an off state while the power is turned on. Therefore, a leakage current can be prevented from flowing to a word line (WL1) through the fault bit line pair (BL1a, BL1b) and a memory cell (1--1). In this way, increase of power consumption due to a short-circuit between bit lines and between word lines can be prevented.
Also, a static type transfer gate sequential circuit is disclosed in Japanese Laid, Open Patent Applications (JP-A-Heisei 5-122020 and JP-A-Heisei 5-122021). In these references, the static type transfer gate sequential circuit is connected between CMOS logic circuits and is composed of a transfer gate (TG), two inverters (V1, V2), an input terminal (D), an output terminal (QB), and a clock input terminal (CC). One of terminals of the transfer gate (TG) is connected to the input terminal (D), and the other terminal is connected to an input terminal of the inverter (V1). The output terminal of the inverter (V1) is connected to the output terminal (QB) and the input terminal of the inverter (V2) whose output terminal is connected to the input terminal of the inverter (V1). In this reference, a resistance value in the signal path is adjusted in the viewpoint of the operation speed. In this way, the static type transfer gate sequential circuit can operate at same high speed as that of a dynamic type, as well as can cope with a low speed operation.
Also, a logic circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-29834). In this reference, a lower threshold voltage logic circuit is connected between a higher potential side quasi power supply line and a lower potential side quasi power supply line. A higher potential side actual power supply line and a lower potential side actual power supply line are connected to the higher potential side quasi power supply line and the lower potential side quasi power supply line through higher threshold voltage transistors (TS1 and TS2), respectively.
Also, a D-type flip-flop circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-202647). In this reference, a CMOS transfer gate for feeding back in the flip-flop circuit is not used. The CMOS flip-flop circuit is connected to a higher potential side power supply line and a lower potential side power supply line via a p-channel MOS transistor and an n-channel MOS transistor.